Low Capacitive Via Path Through High Dielectric Constant Material
Original Publication Date: 1980-May-01
Included in the Prior Art Database: 2005-Feb-13
Some electrical designs for chip packaging specify that the voltage lines have decoupling capacitors as near to the chips as possible. To accomplish this with least inductance between the chip and capacitor, the capacitor should ideally be, in a multilayer structure, directly below the chip, and of a material having a high dielectric constant (K). However, signal vias, which must also be located below the chip, should go through low dielectric constant material.