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Control Generator Disclosure Number: IPCOM000055012D
Original Publication Date: 1980-May-01
Included in the Prior Art Database: 2005-Feb-13

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Related People

Jones, RE Wood, DH [+details]


Shown is a block diagram of a control generator for the generation of control data for memory testing in a programmable tester. The following terminology is employed in the description: S/R 16-bit recirculating shift register CTR 12-bit binary count-down counter SPM single pulse mode circuitry D latch edge-triggered data latch with S1 (strobe 1) on the clock input and 52 on the clear input.