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Self Alignment Method in Integrated Semiconductor Technology

IP.com Disclosure Number: IPCOM000055026D
Original Publication Date: 1980-May-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Berger, HH [+details]

Abstract

Self alignment methods use a mask image exceeding the desired geometry by at least the alignment tolerance. The actual edges of the geometry are determined by structures previously formed on the semiconductor surface. Such structures occur on the boundary between a highly doped N+ region and a slightly doped N- or a P region when the semiconductor surface is oxidized at a suitable temperature. The thickness of the oxide layer formed over the N+ region during oxidation is essentially greater than over the N- or P region. The resulting step in the oxide layer is used for the self alignment of subsequent masks.