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This LSSD (level sensitive scan design) system allows data to be checked at various points in the shift register string 10 without shifting the data through the chain.
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This LSSD (level sensitive scan design) system allows data to be checked at
various points in the shift register string 10 without shifting the data through the
Normally, an LSSD system has two clocks, a B clock which is shared with the
logic and an A clock which cannot be used while the logic is active. In addition,
there is a data input line and a data output line to the string 10. Data is placed
into the string on the data-in line to interrogate the system logic 12. Responses
by the system logic are taken off the string 10 at the data-out line.
A selector tree 14 has been added to interrogate the chain 10 at various
points along its length, or directly interrogate the system logic and a C and D
clocks have been added to operate the selector tree 14. Addresses of the points
along the string can now be placed on the data-in line and fed to a shift register
16 which addresses the selector tree 14. The D clock is held positive as long as
the system is operated in the usual LSSD mode. However, when a selector tree
14 is to be used, the D clock is driven negative to allow the address to pass into
the address shift register 16.
Shifting of the shift register 16 is accomplished using the C clock. This
addresses one of the positions in the chain, thereby passing the data at that
position out into the output gate 18. Since the D clock is negative, the output of
the selector tree 14 is selected instead of the shift register 10.