Exact Simulation of the Pipeline in a Pipelined Processor
Original Publication Date: 1980-May-01
Included in the Prior Art Database: 2005-Feb-13
When a processor is based on a pipeline which does not guarantee the results of every instruction are available to the next sequential instruction, whatever it may be, simulation of that processor by another processor requires exact simulation of the pipeline rather than just functional simulation of the instruction set. Features of the simulation are as follows: 1. Simulation of instructions at the processor cycle level rather than the instruction function level. 2. Ability to simulate the internal details of the processor.