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Described and illustrated is a technique for generating an odd number of stages of ripple clock from a two-phase input clock using a minimum number of logic gates.
English (United States)
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Five-Stage Ripple Latch Lock
Described and illustrated is a technique for generating an odd number of
stages of ripple clock from a two-phase input clock using a minimum number of
A ripple latch clock is a digital circuit with two-phase clock inputs and a
number of outputs. At a precise interval, one and only one of the outputs
changes state. As the circuit runs, all the outputs go high in succession, then go
low in succession, then go high in succession, infinitum.
An earlier article [*] described a four-stage ripple latch clock. The type of
circuit there described lends itself to applications involving an even number of
stages, but cannot accommodate odd numbers of stages as in a divide-by-five
Fig. 1 is a circuit embodying the recognition that each latch
has to be set with one input phase clock and reset by the other input
phase clock and that each successive stage would have to alternate in
its application of phase one and phase two to the set and reset
terms. 1. PH1 is applied to the set term, and PH2 is applied to the
reset term, of latch A. 2. PH2 is applied to the set term, and PH1 is applied to the
reset term, of latch B. 3. PH1 is applied to the set term, and PH2 is applied to the
reset term, of latch C. 4. PH2 is applied to the set term, and PH1 is applied to the
reset term, of latch D. 5. PH1 is applied to the set term, and PH2 is applied to the
reset term, of latch E.
Fig. 2 shows signals A through E produced from PH1 and PH2 in...