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This circuit eliminates any possible contention between a Read/Write Cycle or Refresh Cycle in a processor storage environment.
English (United States)
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Read Write Refresh Cycle Interlocking Circuit
This circuit eliminates any possible contention between a Read/Write Cycle
or Refresh Cycle in a processor storage environment.
The circuit is useful in conjunction with a random-access
memory requiring refresh of the cells to maintain data integrity.
Maintaining this data integrity is accomplished by allowing the
processor to take a refresh cycle at predetermined intervals of time.
During each refresh cycle, any attempt to take a Read/Write Cycle,
and vice versa, needs to be locked out. The circuit shown in the
drawing performs the lockout function. The contention-resolving
circuit is part of the storage interface circuitry located within the
main storage unit. Two interlocking latches are represented. Blocks
1, 2, 3, and 4 form a Red/Write Cycle latch, and blocks 5, 6, and
7 form a Refresh Cycle latch. The circuits operate as follows:
Read/Write Cycle. When the input conditions on lines 8 and 9
to AND circuit 10 are satisfied, its output is transmitted to AND
circuit 1 which provides a set signal for the Read/Write Cycle latch.
The occurrence of a cycle steal or processor storage cycle request
is indicated by the input signal line 8 going to a binary zero value.
If the Start Trigger signal on line 9 is off, this causes a setting
of the Read/Write Cycle latch. OR circuit 3 now becomes active and
degates AND circuit 6 and inhibits any attempt by the interface to
take a refresh cycle. Inverter 4 inverts the output from...