Browse Prior Art Database

Vertical JFET Compatible with Bipolar Processing

IP.com Disclosure Number: IPCOM000055187D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Bergeron, DL Potter, MD [+details]

Abstract

Many high speed bipolar memories incorporate cross-coupled transistors in an emitter-coupled logic configuration. However, it has been found in such cells that the cell standby read power must be decreased in order to improve chip performance. It has also been found that improvement in performance can be achieved by fabricating switched load resistors or parallel diode loads, both requiring additional processing.