Browse Prior Art Database

Elimination of Inter-Plane Shorts in Multilevel Packages

IP.com Disclosure Number: IPCOM000055212D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Dougherty, WE [+details]

Abstract

The use of thin dielectric layers (< 12 Mu) over large areas (90-130 Mu) in multilayer device metallurgy necessitates a highly reliable method of insuring against interlevel shorts. Pin holes in the dielectric will result in an unwanted connection between two metal planes when the second plane is metallized. This "shorting" condition may be minimized when either or both planes contain a low metal to insulator ratio as would be the case with signal planes, since the chance of metal over metal at the pin hole position is statistically low. When voltage planes oppose each other (Vt + Vc), the chances of a pin hole in the dielectric at a position where it would contact both planes is sufficiently large to warrant a method whereby this shorting condition should be rectified.