Tunneling Junction Bipolar Transistors in a Double EPI Process
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13
Inadachi et al recently presented, in an article entitled "A 6ns 4Kb Bipolar RAM Using Switched Load Resistor Memory Cell," ISSCC 1979, pp. 108-9, a very high performance random-access memory using a double epi process. It is shown here that the double epi process has yet one more advantage. It can provide good tunneling junction bipolar transistors. The process is also obviously well suited for implementing good vertical PNP transistors.