Browse Prior Art Database

CCD Loop Synchronization Catch-Up Scheme

IP.com Disclosure Number: IPCOM000055225D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Aichelmann, FJ Enright, CJ [+details]

Abstract

In paging storage systems employing charge-coupled device (CCD) memory loops, only those chips which contain the selected chips are accessed at the faster clock frequency. The remaining chips have their loops recirculating the data at a reduced clock frequency to maintain a reduced power consumption. As a result, when the data transaction has been completed, the selected and unselected loops are not synchronized to the same starting point due to the elapsed time with two different operating clock frequencies. In order for the system to be resynchronized the fast loops must continue after the cast data transmission (i.e., catch up) and then overtake the rest of the system operating off the slower clock.