Indirect Measurement of Storage Access Time
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13
Computer design specifications for semiconductor chip circuits generally require that the access time of a storage array be no longer than the signal transfer time of, for example, nine logic elements connected in series. A simple method of testing used for this purpose compares the signal time lag between the input/output of the storage array with the signal transfer time of nine logic elements of the same chip. According to Fig. 1, address information on lines 1 of storage array 2 transfers data from the output of storage array 2 via conditioned AND circuits 4 and lines 5 to register 6. The output of register 6 is tested on lines 12.