Browse Prior Art Database

Multiple Input Stage

IP.com Disclosure Number: IPCOM000055234D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Pollman, K Remshardt, R Schettler, H Zuehlke, R [+details]

Abstract

During the manufacture of monolithically highly integrated semiconductor storage units the appertaining logic circuits together with the storage are integrated on a semiconductor chip. As a result, storage 2 (Fig. 1) is embedded between input logic 1 and output logic 3. This means that the storage output signals are only available on output pads 5 after they have passed output logic 3 and the following driver stages 4. For test purposes, however, the storage output signals have to be applied to driver stages 4 without passing output logic 3. Therefore, each storage output is connected to its driver stage 4 via a controllable switch 6. Similarly, each output of output logic 3 is connected to the appertaining driver stage 4 via a controllable switch 7.