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Redundancy Scheme for Embedded Arrays

IP.com Disclosure Number: IPCOM000055237D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Brosch, R Klink, E Schettler, H Zuehlke, R [+details]

Abstract

The redundancy scheme described permits the electronic correction of one or several defective bits by means of different substrate part numbers. The scheme is particularly suitable for logic-embedded memory arrays and leads to considerable improvement of the yield. B On a chip, an additional redundant bit is added to each group of, say, 9 bits. It is assumed that the output of the random-access memory is fed directly to the chip logic. For switching off the defective bit, in whose place the redundant bit provided for that purpose is switched on, a decoder circuit is used. The input information of the latter circuit is externally applied, so that only few pins are required for each chip level.