Single Error Correction in CCD Memories
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13
Fig. 1 shows the known serial-parallel-serial (SPS) structure of a charge-coupled device (CCD) storage loop. Each of the two shift registers SR1 and SR2 contains, for example, 32 data bits, and each of the channels connecting the two shift registers has a capacity of, for example, 128 data bits. The proposed memory comprises an additional channel to accommodate a loop parity bit P(L) for each of the 32 data bits.