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A voltage-controlled inversion layer FET capacitance for generating an accurate turn-off point and a fast output signal is introduced into a conventional delay circuit for very long delays.
English (United States)
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Delay Circuit with Voltage-Controlled FET Capacitance
A voltage-controlled inversion layer FET capacitance for generating an
accurate turn-off point and a fast output signal is introduced into a conventional
delay circuit for very long delays.
Fig. 1 shows a conventional bootstrap driver stage with FETs 1 and 2, which
is charged via a transmission stage with FET 3. When the input goes to the up
level, FET 5 turns on and FET 6 starts discharging node A until the gate of FET 2
reaches its threshold voltage VT. At that point, T2 turns off, and bootstrapping of
FET 1 and CB can be effected in a conventional manner, causing the output
potential to rise. Previously, a fixed capacitance was associated with node A, and
the time constant, and thus the effective delay time, was determined in
conjunction with FET 6. The improved circuit of Fig. 1 uses a voltage-controlled
inversion layer capacitance represented by FET 8, the source and drain
connection of which is pumped up to an appropriate voltage Delta V by the input.
This is shown in general in Fig. 1, according to which the voltage source,
containing FET 4 and resistor R, is connected to a suitable voltage VI.
The operation of the circuit of Fig. 1 is shown in the timing diagram of Fig. 2.
It is assumed that the respective starting conditions are set by precharging or
restoring (pulse R, FET 7). If node A is discharged to VT + Delta V during the
delay phase, the capacitive portion of the effective discharge time consta...