Browse Prior Art Database

Delay Circuit with Voltage-Controlled FET Capacitance

IP.com Disclosure Number: IPCOM000055240D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Arzubi, L Baier, E Loehlein, WD [+details]

Abstract

A voltage-controlled inversion layer FET capacitance for generating an accurate turn-off point and a fast output signal is introduced into a conventional delay circuit for very long delays.