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Double Polysilicon Electrically Alterable Read-Only Storage Cell

IP.com Disclosure Number: IPCOM000055245D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Hsieh, YN Kluga, DA Wang, PP Wood, RA [+details]

Abstract

Fig. 1 shows a two-device memory structure including a conventional field-effect transistor 11, used for word line selection, and a floating gate memory device 13. Transistors 11 and 13 are connected in series between the bit line Y and the source S. The memory device 13 can be written by means of channel hot electron injection when voltages in the order of 20 to 24 volts gate to source and 10 to 12 volts drain to source are applied to the gate G and drain Y simultaneously. The cell can be erased by means of hot hole injection from drain or source substrate junction avalanche breakdown. Avalanche breakdown away from the channel at the source substrate junction is preferable in order to avoid accumulating trapped holes in the channel region. Trapped holes hinder subsequent channel injection of electrons to the floating gate.