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This detection scheme can be used to verify the presence of I/O pins in a closely spaced array.
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I/O Pin Array Integrity Detector
This detection scheme can be used to verify the presence of I/O pins in a
closely spaced array.
A one for one replica 10 of I/O pin array configuration is shown in the figure.
The replica is lowered via guide pins 12 and 14 onto an I/O pin array. As the I/O
pins contact their respective detection features 24 on the replica, unaligned pins
will be detected.
The holes 16 and the detection features 24 in the replica are
along a non-metallized path 18 between two metallized segments 20 and
22 powered by (+) and (-) potentials, respectively. If the I/O pins
do not lift their respective detection feature head 24 above the (+)
and (-) potentials, the head will remain in contact with both
metallized segments, thereby shorting out the (+) and (-) potentials.
A light connected across the segments can be used to detect the
bridging by one or more of the detection heads.
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