Deferred Cache Storing Method
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13
A method is described that provides for faster execution of typical instruction sequences. This is accomplished by reducing the interference in storage between writes (the storing of data) initiated by one instruction and data fetches for subsequent instructions. The method was developed for a processor in which a write operation can delay subsequent fetch operations. In particular, it is applicable to pipelined or overlapped machines which attempt to fetch operands for the next several instructions while they are doing the write for a previous store instruction.