Browse Prior Art Database

Local Working Store Array

IP.com Disclosure Number: IPCOM000055269D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Letteney, RC Levine, SR Maass, KK [+details]

Abstract

The floating-pointy registers of an IBM System/370 processor are registers 0, 2, 4 and 6 of 4-32x18 arrays configured as 32 registers by 72 bits wide. This configuration in the execution unit is called local working store (LWS) 1. The 32x18 array is an array with only one data bus out (read one address at a time). The RR-format floating-point add, subtract, and compare instructions require the reading of both operands' exponents since the exponent compare is the first operation that has to be performed. The solution to this problem is to provide another array 2 (EXPLWS) * which holds the exponents (bits 0-7) and whose parity PO is always * identical in value to the exponent in local working store 1.