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Zero Delay Set Reset Latch with Edge-Triggered Strobe Control

IP.com Disclosure Number: IPCOM000055299D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Marino, PT [+details]

Abstract

Highly responsive strobe and latch circuits are necessary in integrated circuit applications for performing high speed logic functions. The drawing shows a D-type latch constructed of a set/reset (S/R) latch and a single-ended strobe input circuit. A set of current sources provides uniform bias currents for operating the illustrated circuits in a known manner. The "D" input is supplied to an inverter which in turn is coupled to a pair of differential AND circuits A1, A2 which are clocked and provide data strobe for setting and resetting the S/R latch. The S/R latch employs a differential amplifier employing positive feedback, as shown. The set input is via the dot OR circuit, while the reset input is to the dot AND circuit from A1.