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A differentially operated latch has a single logic block delay, uses minimal components and energy, and employs current mode logic. The latch is timed by a clock and has a comparator input stage.
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Differentially Operated Latches
A differentially operated latch has a single logic block delay, uses minimal
components and energy, and employs current mode logic. The latch is timed by
a clock and has a comparator input stage.
Transistors T3, T4, T5 and T6 make up a differential comparator. T7 and T8
are cross-connected to latch the output of the differential comparator as timed by
the clock. When the clock is negative, current source I1 obtains current through
T1 to activate the comparator stage. When the clock goes positive, the I1 current
flows through T2 for energizing the latch T7, T8. The energized latch captures
the output of the comparator at the clock transition time and thereby ignores any
intervening transitions on the input signal, i.e., when the positive clock is actually
positive. The clock is of the differential type; that is, when the minus clock is
negative, the plus clock is positive, and vice-versa. Accordingly, I1 energizes
both the comparator stage and the latch by combining the comparator stage with
the latch T7, T8, as shown. A minimal circuit delay is achieved. Switching the I1
current between the comparator and the latch achieves a minimal switch time.
The latch can be cascaded into a shift register. Latches L1, L2
interconnected and timed, as shown, create a high speed shift register.
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