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Floating-Duplex Decode and Execution of Instruction

IP.com Disclosure Number: IPCOM000055331D
Original Publication Date: 1980-Jun-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Miller, RE Shen, DT Sun, RC [+details]

Abstract

A technique is described herein for speeding up the operation of a computer by concurrently executing pairs of consecutive instructions which are data-independent. Two instruction units are used which share one arithmetic unit. Both pipelined and non-pipelined versions are discussed. The technique is generally applicable to central processing unit design to speed up performance, and differs from pipelined control.