Browse Prior Art Database

A Wire Through Logic Cell in CFET Polysilicon Technology Utilizing Slidable Polysilicon Contacts

IP.com Disclosure Number: IPCOM000055350D
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Allesandrello, TP Kraft, WR Moore, VS Rhodes, JC Stahl, WL Thoma, NG [+details]

Abstract

The cell layout shown in the figures allows a master slice Weinburger layout to be utilized in polysilicon logic technology. The advantage of being able to run metal wire over a polysilicon gate allows the polysilicon contact to slide to the left or to the right to be aligned with a first level of metal running vertically. This structure allows powerful wiring algorithms to be used in computerized designs and layouts using polysilicon logic devices.