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By adding the circuitry enclosed by dotted lines in the drawing, the double inverter circuitry now operates as a polarity hold latch.
English (United States)
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Monolithic Polarity Hold Latch
By adding the circuitry enclosed by dotted lines in the drawing, the double
inverter circuitry now operates as a polarity hold latch.
When the clock is near ground, T23 is off. With the input up, current through
R1 is steered through the base of transistor T1, turning it on. This, in turn, steers
current through R2 into the base of T4, turning T4 on. With T4 on, T5 is turned
By raising the clock, the "2" side of transistor T23 is turned on, since the "3"
side is connected to the off transistor T5, and is, therefore, off. With the "2" side
of T23 on, this keeps current flowing through R2 and, therefore, into the base of
T4, which preserves the state of the latch. The input no longer has control over
transistor T4 or T5.
When the input and clock are down, transistor T1, T23 and T4 will be off and
T5 will be on. Current passes through R4 into the base of T5. The rising clock
now turns the "3" side of transistor T23 on. This transfers the current through to
transistor T5, and keeps transistor T4 off. Again the input loses control for the
potential at the base of transistor T1 is clamped by its collector-base junction.
Therefore, the state of transistor T4 and T5 is preserved with the rising edge of
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