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Shift Register Data Deserialization Without a Counter Disclosure Number: IPCOM000055375D
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13

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Schaadt, RA [+details]


In the above circuit, the deserialization of a byte is initiated by the start pulse applied to OR 10 at slave clock time. The clock pulse through OR 10 resets all stages of a shift register 12 except the first stage which is set. The set condition of the first stage acts as a marker which shifts through the shift register to determine when deserialization is complete.