Hard coupled Sandwiched High Density Floating Gate Cell
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13
A floating gate memory cell is provided having a three-plate capacitor above a semiconductor substrate to increase the coupling between the floating gate and a control or writing electrode, reducing the need for high operating voltages, while neutralizing parasitic capacitances. The control gate is located between the floating gate and the semiconductor substrate.