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Integrated Logic Array Disclosure Number: IPCOM000055422D
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13

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Barish, AE Ehrlickman, RL [+details]


Combining logic and array on the same masterslice creates several problems, the most noteworthy being: 1. A fixed portion of the masterslice silicon must be dedicated to the array and is not available for random logic. 2. The physical size of the array is predetermined by the area dedicated to it and not readily changed. 3. The automatic wiring programs are constrained since the array cannot be optimally placed for individually wired user part numbers.