Browse Prior Art Database

Digital Single-Shot

IP.com Disclosure Number: IPCOM000055434D
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Cukier, M [+details]

Abstract

The counter shown in Fig. 1A comprises a shift register (SR) and an exclusive-OR circuit (XOR) providing a feedback value to the input of the register, which depends on the binary values in the two last stages of the shift register. Assuming that the initial state of the shift register is 0001, the successive states of the register will be: 1000, 0100, 0010, 1001, 1100, 0110, 1011, 0101, 1010, 1101, 1110, 1111, 0111, 0011, 0001. Thus, the counter describes the loop 1, 8, 4, 2, 9, C, 6, B, 5, A, D, E, F, 7, 3, 1, representing the hexadecimal notations of the binary states. If the initial state of the shift register is 0000, the state will remain equal to 0000. The behavior of the counter is represented in Fig. 1B. There are two independent loops, one of 15 different states and the other of only one state.