Browse Prior Art Database

Electrically Alterable Memory Cell with Independent Erase Input

IP.com Disclosure Number: IPCOM000055450D
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Hsieh, YN Kluga, DA Wang, PP Wood, RA [+details]

Abstract

Floating gate FET devices provide electrically programmable and erasable non-volatile (EAROS-electrically alterable read-only storage) memory cells. The devices are programmed to a high threshold state by 'hot' carrier electrons generated in the device channel and injected across the gate oxide to the floating gate. Erasure is achieved by either of two methods: (1) compensation of the negative charge with holes generated by the avalanche breakdown of a diffusion junction in close proximity to the floating gate and (2) field emission of the electrons directly across a thin insulator region between the floating gate and an underlying diffusion.