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Parity Check Circuit for Adder with Shared Logic

IP.com Disclosure Number: IPCOM000055453D
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Kaufman, DR Thompson, GR [+details]

Abstract

The drawing shows two stages of an adder that each receive corresponding bits A and B of two terms to be added and the carry from the previous stage and produce a sum S and a carry out C(out) to the next stage. The operation of the adder can be checked by parity circuits. Since each sum is the three-way exclusive-OR function of A, B and C(out) from the previous stage, the parity of the sums should equal the parity of the two words to be added and the carrys.