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This article describes a technique which allows the implementation of a testable AC trigger which complies with all requirements of Level Sensitive Scan Design (LSSD).
English (United States)
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LSSD Testable AC Trigger
This article describes a technique which allows the implementation of a
testable AC trigger which complies with all requirements of Level Sensitive Scan
An implementation of a single AC trigger and the necessary "C" clocks
(Alpha, Beta and Gamma) is illustrated in Fig. 1. The trigger includes three shift
register latches AA, AB and AC. During operation, the C clocks Alpha, Beta and
Gamma are forced on by the tie-up being high, and the L1 latches operate as
standard set/reset latches. Under this condition the circuit is equivalent to a
standard NOR logic AC trigger (illustrated in Fig. 2). The L1 latch of AA in Fig. 1
is the equivalent of blocks AA and AB of Fig. 2, the L1 latch of AB is equivalent to
BA and BB, while AC is equivalent to CA and CB of Fig. 2.
The scan lines and LSSD clocks were omitted from Fig. 1 for clarity. The L2
latches of AA and AB are used for scan only, while the L2 latch of AC is used for
the LSSD synchronized output.
During testing, the external tie-up is changed to low, and since the C clocks
(C, C' and C") are selected to be nonoverlapping or independent, no LSSD rule is
violated and the circuit under this condition is testable.
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