Interval Timers Implemented with Virtual Address Translation Apparatus
Original Publication Date: 1980-Jul-01
Included in the Prior Art Database: 2005-Feb-13
Interval timers, time of day clock and clock comparison are implemented in a computer system (Fig. 1) by utilizing virtual address translation (VAT) 30 apparatus and data paths instead of dedicated hardware or dedicated microcode. The use of virtual address translation apparatus is possible because this apparatus can complete its operation faster than the translation requirement. This is because main storage accesses are slower than the virtual address translation apparatus and translation look ahead is not possible in this instance because commands are not buffered. Hence, there is idle time in the virtual address translation apparatus, and this idle time enables the virtual address translation apparatus to be used for timer functions.