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The latch shown in the drawing has a reduced pulse width and provides a non-clamped output. Transistors T2 and T3 are base to collector cross-coupled transistors.
English (United States)
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High Speed Latch
The latch shown in the drawing has a reduced pulse width and provides a
non-clamped output. Transistors T2 and T3 are base to collector cross-coupled
In the stand-by state, clock C is inactive so that diode D1 conducts, which
turns off transistor T1, thus inhibiting the input data. An output at "1" level is
obtained by allowing transistor T1 to be conductive (data at "0", clock active),
whereas an output at "0" level is written by cutting off all the input transistors T1,
T4 and T3.
Transistor T6 is inserted to solve the clamping problem of conventional
latches. Thanks to T6, the swing of DC voltage to reach the threshold of
transistor T4 is smaller so that with output data at "0", it takes less time to bring
T4 to conduction in order to hold a "1" at the output. Furthermore, the speed is
also improved by means of diode D2, as transistor T6 will be cut off rapidly since
it is controlled at its base via diode D2 and at its emitter via the output.
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