Browse Prior Art Database

Fast Data Access in a CTS Cell Matrix Memory

IP.com Disclosure Number: IPCOM000055644D
Original Publication Date: 1980-Aug-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Boudon, G Denis, B [+details]

Abstract

In a memory comprising CTS (complementary transistor switching) cells, such as Cij, connected to up word line UWLi and down word line DWLi, and to bit lines LBLj and RBLj to build up an array of n x m cells, write and read circuits 1 and 2, respectively, allow the data access delay and the dissipated power to be reduced.