TTL Level Controlled FET Transfer Circuit
Original Publication Date: 1980-Aug-01
Included in the Prior Art Database: 2005-Feb-13
This transfer circuit comprises a transmission field-effect transistor T1, with the drain representing input I and the source output 0, for a a pulse with a relatively high amplitude (FET level). A control circuit connected to the gate determines the ON and OFF states of T1 as a function of a control pulse S with a relatively low amplitude (TTL level). Thus, a driver pulse capable of driving high capacitive loads is passed or retained by the transfer circuit, using a low-duty control pulse S.