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A storage expansion scheme is provided to access consecutive blocks of 16K bits of storage, allowing the lower boundary of the block to be positioned at 4K-byte increments.
English (United States)
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A storage expansion scheme is provided to access consecutive blocks of
16K bits of storage, allowing the lower boundary of the block to be positioned at
The storage expansion system is applicable to an 8-bit microprocessor
wherein it is desired to expand storage to larger than the 64K bytes offered. The
hardware required to expand the storage space to 1 megabyte is shown. It
consists of an AND gate 11, an 8-bit page register 13, and an 8-bit adder 15.
Page register 13 is loaded by microprocessor 17 with an 8-bit value. The
microprocessor 17 also outputs 16 address lines. During a memory cycle when
the highest address lines ADR14 and ADR15 are both true, the content of the
page register 13 is added to the four most significant bit address lines (ADR12 -
ADR15) to form an 8-bit output. This 8-bit output is combined with twelve
unaffected address lines (ADR0 - ADR11) to create a 20-bit address, thus
allowing access up to 1 megabyte of storage.
With this scheme, the low 48K memory space is not affected because
address translation occurs only when the upper two address lines are true.
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