Performance Enhancement for the AH, CH, MH and SH Instructions
Original Publication Date: 1980-Aug-01
Included in the Prior Art Database: 2005-Feb-13
IBM System/370 architecture requires for certain halfword (HW) instructions (i.e. Add Halfword, Compare Halfword, Multiply Halfword and Subtract Halfword) that the 16-bit signed integer (the second operand) be expanded to 32 bits before the operation is effected. This operand expansion is done by propagating the sign-bit value through the 16 high-order bit positions.