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Performance Enhancement for the AH, CH, MH and SH Instructions

IP.com Disclosure Number: IPCOM000055675D
Original Publication Date: 1980-Aug-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Angiullli, JM Chang, DC Zajac, MW [+details]

Abstract

IBM System/370 architecture requires for certain halfword (HW) instructions (i.e. Add Halfword, Compare Halfword, Multiply Halfword and Subtract Halfword) that the 16-bit signed integer (the second operand) be expanded to 32 bits before the operation is effected. This operand expansion is done by propagating the sign-bit value through the 16 high-order bit positions.