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Long Line Receiver

IP.com Disclosure Number: IPCOM000055815D
Original Publication Date: 1980-Sep-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Chan, YH Klara, WS Vicary, CE [+details]

Abstract

The long line receiver was designed as an interface between the memory and logic circuits of a computer system. This receiver is driven by memory circuits supplying voltage levels of -1.35 volts and ground and itself drives logic circuits requiring voltage levels of ground and +2.4 volts. The receiver is wired on a semiconductor logic chip using the devices normally used to implement a logic circuit. As illustrated in Fig. 1, the receiver utilizes two Schottky barrier diodes (S1 and S2) for extended fan-in capabilities. Transistors T1 and T2 together with the Schottky barrier diodes provide the proper threshold and AND-INVERT logic function. Base drive is supplied in the conventional manner through resistor R3.