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Lay Out of an Emitter Coupled Cell with PNP Loads

IP.com Disclosure Number: IPCOM000055823D
Original Publication Date: 1980-Sep-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Boudon, G Denis, B Mollier, P [+details]

Abstract

Fig. 1A shows a memory cell comprising emitter-coupled transistors T1 and T2 as a Harper cell, PNP transistors T and T$ arranged as collector loads instead of resistors, and Schottky barrier diodes SBD1 and SBD2. Thus, the standby current is reduced without impairing the noise immunity of the cell.