Browse Prior Art Database

Lay Out of an Emitter Coupled Cell with PNP Loads Disclosure Number: IPCOM000055823D
Original Publication Date: 1980-Sep-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue


Related People

Boudon, G Denis, B Mollier, P [+details]


Fig. 1A shows a memory cell comprising emitter-coupled transistors T1 and T2 as a Harper cell, PNP transistors T and T$ arranged as collector loads instead of resistors, and Schottky barrier diodes SBD1 and SBD2. Thus, the standby current is reduced without impairing the noise immunity of the cell.