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The circuit shown in Fig. 1 is to be used as a word decoder/driver in a memory having a low power supply. At low power supply voltage, a Darlington scheme cannot be used as a word driver.
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Memory Power Down Circuit and Word Line Decoder/ Driver under Low
The circuit shown in Fig. 1 is to be used as a word decoder/driver in a
memory having a low power supply. At low power supply voltage, a Darlington
scheme cannot be used as a word driver.
Referring to Fig. 1, the word driver T2 turns "on" and supplies a high current
to the cells, when the word is selected. A clamping transistor T3 is used to
define the word line voltage when selected. When a word is not selected, T1
turns "on", and thus T2 turns "off", with T1 supplying the standby current of the
cells. The total circuit power dissipation is thus drastically reduced, using only
NPN transistors. By using a 1 K omega base resistor (R2) in the word driver, the
selection speed of the word line is quite high although a high current (10 mA) has
to flow through T2.
The diagram in Fig. 2 shows the voltages at nodes 1, 2 and on the word line
when selected and when not selected.
This type of circuit may be used to reduce the total power consumption of a
chip by means of a "chip select" control C/S, as shown in Fig. 3.
The first stage of the schematics shown in Figs. 1 and 3 is a current switch
decoder, well suited for this application, but any other type of decoder can be
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