Asynchronous Command Prioritization
Original Publication Date: 1980-Sep-01
Included in the Prior Art Database: 2005-Feb-13
A processor to processor interface (PPI) arrangement is provided where synchronization of commands from two processors is achieved by giving priority to the command from the processor that raises its CONTROL OUT signal first, provided the other processor is not already executing a command to the processor to processor interface. The processor to processor interface determines which processor was the first to activate its CONTROL OUT signal. When processors issue commands simultaneously to the processor to processor interface, a SERVICE IN signal is activated only to the processor receiving priority. The processor has finished execution of its command. SERVICE IN signal to the other processor is delayed until the first processor has finished execution of its command.