Browse Prior Art Database

Processor to Processor Data Transfer Control

IP.com Disclosure Number: IPCOM000055887D
Original Publication Date: 1980-Sep-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Booth, RC [+details]

Abstract

Data transfer control logic controls the transfer of data from one processor to another processor under cycle steal control. Host processor 10 (Fig. 1) can transfer data to I/O processor 100 via processor to processor interface (PPI) 50, or I/O processor 100 can transfer data to host processor 10 via processor to processor interface 50. The processor to processor interface 50 contains the data transfer control logic and effects the data transfer after initialization without any further control from either processor 10 or processor 100.