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This article describes a low power buffer circuit which may be employed in a static random-access memory structure as an output buffer. The advantages of this buffer circuit are low power and simplicity.
English (United States)
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Low Power Buffer Circuit
This article describes a low power buffer circuit which may be employed in a
static random-access memory structure as an output buffer. The advantages of
this buffer circuit are low power and simplicity.
The output buffer circuit is illustrated in schematic form in the drawing. Inputs
SA and SA to the buffer are from a sense amplifier, and the buffer outputs go to a
push-pull driver stage. In the off or idle state, inputs SA and SA are both high.
Buffer outputs B and B are both low, and the tri-state push-pull output is floating.
As long as inputs SA and SA remain high, the buffer outputs B and B will be
clamped low by devices 7 and 8 and both pull-up load gate voltages L3 and L4
will be clamped low by devices 5 and 6. During this portion of the cycle, there is a
small power being dissipated in depletion load devices 1 and 2. As soon as the
sense amplifier is set, one of the sense amplifier outputs SA and SA will begin to
fall, causing either one of the devices 5 and 6 which are clamping the L3 and the
L4 nodes, respectively, to turn off.
Assume SA goes low. Since device 6 is off, node L4 will charge through load
device 2. As node L4 charges, device 4 will turn on, causing node B to rise. B
going high clamps node B low through device 9 and clamps node L3 low through
device 11. The only power dissipated in the buffer current is in the small load
device 1. The large pull-up devices 3 and 4 do not dissipate DC power during
any portion of the...