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Fast Resolution of Condition Code for Some Logical Operations Disclosure Number: IPCOM000055937D
Original Publication Date: 1980-Sep-01
Included in the Prior Art Database: 2005-Feb-13

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Sachar, H [+details]


In the Fixed Point Unit, instructions requiring calculation are processed by decoding and staging their operands in the A and B registers during the first cycle and executing the calculation and depositing the results in a C register in the second cycle.