Browse Prior Art Database

FET to T/2/L Interface Receiver

IP.com Disclosure Number: IPCOM000056017D
Original Publication Date: 1980-Oct-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Chan, YH Klara, WS Vicary, CE [+details]

Abstract

This circuit was designed as an interface between FET memory circuits and T/2/L logic circuits in a computer system. This circuit accepts voltage levels of ground and +5.5 volts and converts them to +0.3 volts and +3 volts. The circuit is fabricated in a semiconductor chip whose P- substrate is connected to -1.5 volts. Since the FET driver circuit can produce voltages as high as +5.5 volts, this circuit was designed such that a collector substrate breakdown voltage limitation of 6.5 volts was not violated. This circuit (Fig. 1) prevents the +7.0 volts from developing across the junction. The two resistors (R1 and R2) in series with the Schottky barrier diode S1 minimize the loading when the voltage at input A0 is at a Down level. The collector base Schottky barrier diode S2 prevents saturation.