Method for Removing High Spots for Planarization of Integrated Circuit Surfaces
Original Publication Date: 1980-Oct-01
Included in the Prior Art Database: 2005-Feb-13
A photoresist process is provided which can be used to planarize integrated circuit surfaces which have large areas as well as small areas. In the process, metallized high spots are removed prior to completion of the planarization process. Known planar photoresist processes have required perfect alignment over areas to be protected or have relied upon photoresist application processes which result in a thin photoresist layer over the large area. The process disclosed herein is independent of mask alignment problems; perfect alignment is not needed, the photoresist does not need to flow completely over the areas to be protected, and overflow of the photoresist which results in bridging is not a problem.