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This is a technique for transferring bits from a serial input register to a parallel section in an serial-parallel-serial charge-coupled device (SPS CCD) with simplified clocking.
English (United States)
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Serial Parallel Serial Charge Coupled Device Serial to Parallel Charge
This is a technique for transferring bits from a serial input register to a
parallel section in an serial-parallel-serial charge-coupled device (SPS CCD) with
In an interlaced SPS CCD memory system, it is known for the
serial input register to have three clocks (01, 0A and 0B), while the
output serial register has two clocks (01 and 02). 0l and 02 are
clocks supplied by the system, while 0A and 0B are generated on chip.
Fig. 1 illustrates a simplified SPS configuration including input
serial register 10, parallel section 12 and output serial register 14.
Described herein is the addition of a transfer gate 16 to provide more reliable
transfer of data from input register 10 to parallel section 12 with simplified
clocking. The arrangement illustrated in Fig. 2 prevents a bit intermix at the input
of register 10. Also, clocking is simplified by eliminating the need for the 0A and
The foregoing is accomplished with the structure illustrated in Figs. 3-5. As
shown in Fig. 3, bits are received at the input terminal and propagated through
the serial input register 10 by means of the 01 and 02 clock pulses. Transfer
gate clock pulses 0IN1 and 0IN2 together with 0TINX transfer the serial bit
stream into the parallel section. The first half of the bits is transferred when 01 is
off and 0IN2 is off. During this time 0TINX is on, and hence the bits are