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In some cases the reduction of switching speed is very attractive. This is especially true in crosspoint arrays where slow transient values are necessary to avoid undesirable triggering.
English (United States)
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Technique for Decreasing Thyristor Switching Speed
In some cases the reduction of switching speed is very attractive. This is
especially true in crosspoint arrays where slow transient values are necessary to
avoid undesirable triggering.
With respect to the standard crosspoint structure, such as described in an
article entitled "Semiconductor Crosspoints" by L. L. Rosier et al, on page 439 of
the July 1969 issue of the IBM journal of Research and Development, consisting
of two transistors and an input RD circuit, the present structure (Fig. 1) adds both
a small correcting resistor R' and a capacitor in parallel with resistor R.
The voltage amplitude on the gate terminal is fixed. The
current entering the transistor T base is limited by the parasitic
C(GK) capacitance value. By adding the R' resistor, this capacitance
is loaded at a lower rate, which results in decreasing the current i.
Calculations show that the anode current I takes the form:
Gamma(1) and Gamma(2) being respectively the carrier transit times of
T and T(2). Thus, the rise time is directly proportional to the i
current. Also, to reinforce this effect a capacitor C is also mounted
in parallel with resistor R.
The whole structure may be optimally integrated (Fig. 2). The Lshaped gate
region, with the gate electrode offset with respect to the gate region, assures the
implementation of resistor R'.
This particular layout design offers several advantages. It decreases the