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Power Supply System for MTL Circuitry

IP.com Disclosure Number: IPCOM000056045D
Original Publication Date: 1980-Oct-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Heuber, K Wiedmann, SK [+details]

Abstract

In accordance with the sectional view of Fig. 3 showing part of a complex MTL (merged transistor logic) circuit illustrated in the plan view of Fig. 1, an MTL basic circuit consists of a P injector 1 and P base 2 with embedded N+ collectors 3 of a vertical transistor powered via the injector. P injector 1 and P base 2 are arranged in N epitaxial layer 4. Layer 4, which is deposited on top of a buried N+ layer 5 on P semiconductor substrate 6, serves as an emitter of the transistor.